해외근무 반도체 DRAM 전문가 초빙

▣ 회사소개
   - 해외기업 으로서 반도체 DRAM 전문기업
   - 해외근무

 (채용공고 등록상 부득이하게 국내로 체크한점 양해를 부탁드립니다. 적임자께 근무지 오픈이 가능하기에...)

▣ 포지션
   반도체 DRAM 전문가 초빙

▣ Job Description
     1. Familiar with Verilog and JEDEC SPEC, and write Direct and Random verilog patterns according to JEDEC spec
     2. Familiar with JEDEC SPEC and write Finesim vector to check the design internal timing margin, as well as Jedec defined input/output timing spec
     3. Faimiliar with Product Testing Flow, and write Verilog and finesim patterns to check all CP/FT program, as well as all Testmodes/Fuses.
     4. Well understand the circuitry, able to trace circuit to find the failure point and feedback to designer
     5. Good Communcation skill with Producat Engineer, able to fully understand the failure signature and use verilog simulation to duplicate the silicon failure mode, trace circuit to the failure point, the feedback to designer

▣ Job Requirement：
     1. Department of Electronic Engineering and over the 13years experience
     2. Able to lead a silicon issue debug group, able to review the pattern coverage and make sure all functions are fully covered.
     3. Able to work with PT team to solve complicated silicon/system issue.
     4. Able to work with CAD to define the design/verification flow.
     5. Fully understand Circuitry and Jedec Spec, thus can fully debug simulation fail point.
     6. Fully understand the circuitry and Familiar with the IC Design milestone & flow.
     7. Able to work with CAD to improve the design/verification flow
     8. Familiar with the IC Product Test Flow and the need of Test Time Reduction.
     9. Understand the design flow and able to build up the verification enviornment.
     10. Able to work with system engineer and debug system related issues

▣ 참고사항
   - 나이제한 없음
   - 연봉 및 처우 충분한 협의가능 조건

▣ 접수방법
    1. 이력서(사진첨부 / 연락처 및 희망 연봉기재)
    2. 자기(경력)소개서(근무회사 소개 및 주요 경력업무 위주로 기재)
    3. 가급적 MS-word 자료를 부탁드립니다.
    ※ 채용마감일이 따로 있지는 않으며 채용시 마감인 관계로 빠른 지원을 부탁드립니다.